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USP-186 offers real-time in-circuit emulation, development and HLL debugging for the entire 80C186 family of chips.
USP-186 comes with full 1 MB of memory, C/C++ and ASM debugger, 80-bit wide by 32K deep trace buffer, and a sophisticated Event Triggering System that uses combinations of address and data comparators, sequencer, external probes, and pass counters to create almost any complex trigger condition.
The zero wait-state, dual-ported memory allows the user full read/write access to the emulation memory, without slowing down the running processor. Because of this unique feature, watching and modifying the variables and parameters can be done without stopping the processor and disrupting the running application.
Selective tracing of only meaningful data is easily achieved with the aid of the event triggering system. A 32-bit time stamp records exact time relationships between instructions and routines in absolute or relative modes with a 100 nsec resolution.
The HLL debugger provides support for Intel, Microsoft, and Borland compilers. Unlimited number of breakpoints and passpoints may be set or cleared with a mouse, by simply clicking on the desired instruction in the source window. You can watch variables change on-the-fly, and zoom in on any member of a complex structure with a click of a mouse.
A build-in hardware Coverage Monitor captures in real-time every program fetch, memory read/write, and I/O read/write transaction. Collecting these transactions may be done individually or in any combination of them to display a map of memory usage and help in finding code that never executes, variable usage, un-initialized memory reads, or illegal memory accesses.
The emulation CPU (either bondout or standard) is mounted on a probe assembly, which plugs directly into the target system, for fast and noise free emulation.
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